1. Field of the Invention
The present invention relates to a spread-spectrum clock generator (SSCG). More particularly, the present invention relates to an SSCG including a voltage-controlled delay line (VCDL).
2. Description of Related Art
Spread-spectrum is a technique for modulating a clock frequency. Frequency of a general non-spread-spectrum clock signal is fixed. Energy of such clock signal is concentrated at a signal spectrum tone, and an electromagnetic interference (EMI) thereof is relatively severe. As to a spread-spectrum clock signal, the energy thereof is dispersed to a plurality of spectrum tones, so that amplitude of each tone is decreased, and the EMI is reduced. FIG. 1A and FIG. 1B illustrate two conventional spread-spectrum methods. FIG. 1A illustrates a down spread method, i.e. spreading towards low spectrums, wherein an original clock signal spectrum is marked as 102, and a spread clock signal spectrum is marked as 101. FIG. 1B illustrates a center spread method, i.e. spreading towards high spectrums and low spectrums simultaneously, wherein an original clock signal spectrum is marked as 104, and a spread clock signal spectrum is marked as 103.
FIG. 2 is a schematic diagram illustrating a typical clock frequency modulation profile, and the modulation profile refers to a variation relation between frequencies of a spread spectrum clock signal and time. The spread spectrum has two main parameters, and a first one is modulation percentage, i.e. a proportion between a maximum frequency variation and an original clock frequency. The profile of FIG. 2 belongs to the center spread, the original clock frequency before spreading is Fcenter, and the modulation percentage is (Fmax−Fcenter)/Fcenter or (Fcenter−Fmin)/Fcenter. A second main parameter is modulation frequency (MF), i.e. a reciprocal of a cycle of the modulation profile, for example, the modulation frequency of the profile of FIG. 2 is FMOD.
FIG. 3 is a schematic diagram illustrating a plurality of conventional clock frequency modulation profiles and corresponding output spectrums. FIG. 3 can be regarded as a 3×2 table, wherein a first column illustrates three conventional modulation profiles including a sine wave, a triangle wave and a Hershey's Kiss, and a second column illustrates spectrums of the clock signal after being spread by the left-side modulation profiles. As shown in FIG. 3, the Hershey's kiss is the optimal modulation profile, and amplitude of the output spectrum thereof is the most uniform and lowest, and the EMI thereof is the most minor.
FIG. 4 is a circuit schematic diagram illustrating a conventional SSCG 400 formed based on a phase-locked loop (PLL). Frequency dividers 401 and 402, a phase/frequency detector 403, a charge pump 404, and a voltage control oscillator (VCO) 405 form the main PLL. A low-pass filter formed by a resistor R1 and capacitors C1 and C2 can moderate outputs of the charge pump 404, so that frequency variation of an output clock signal Fout can be stable. A node 406 receives a triangle wave which controls spectrum spreading of the output clock signal Fout.
Within such an SSCG, a loop bandwidth of the PLL is relatively low, and a loop filter thereof has to be designed rather large, so that the capacitors C1 and C2 may occupy a relatively large area, and the capacitor area is generally one to three times greater than other circuits. Due to the two bulk capacitors, looping time of the PLL is greatly prolonged, which can be 20 times greater than that of a general PLL. Therefore, not only the whole area and cost are increased, but also performance thereof is poor.
FIG. 5 is a circuit schematic diagram illustrating another conventional SSCG 500. The SSCG 500 does not apply the analog PLL structure, but applies a digital serial delay structure. The SSCG 500 includes 200-stage serial connected delay units 511, and each of the delay units 511 includes a latch 512 and an inverter 513 used for changing a delay time. An output terminal Q of the latch 512 controls the delay time of the inverter 513, wherein when an output of the latch 512 is logic 1, the delay time of the inverter 513 is relatively long, and when the output of the latch 512 is logic 0, the delay time of the inverter 513 is relatively short. A multiplexer 521 and an inverter 522 form a control circuit 520, and an output of the control circuit 520 is a signal Q0. The 200 latches 512 of the SSCG 500 are serially connected into a sequence, and the 200 inverters 513 are serially connected into another sequence. During each cycle of an input clock signal Fin, the signal Q0 is shifted to a signal Q200, the signal Q200 is shifted to a signal Q199, and the signal Q199 is shifted to a signal Q198, deduced by analogy, the signal Q2 is shifted to a signal Q1.
At the beginning, the signals Q1 to Q200 are all logic 0, the control circuit 520 sets the signal Q0 to be logic 1, and the input clock signal Fin is processed by the 200-stage inverters 513 to form an output clock signal Fout. After the 200 short delays, the output clock signal Fout then has the shortest cycle and the highest frequency. During a next cycle, the rightmost latch 512 latches the signal Q0, and turns the signal Q200 into logic 1, so that after the input clock signal Fin is processed by 199 short delays and one long delay, the cycle of output clock signal Fout is slightly prolonged, and the frequency thereof is slightly decreased. During a still next cycle, the second rightmost latch 512 latches the signal Q200, and turns the signal Q199 into logic 1, so that after the input clock signal Fin is processed by 198 short delays and two long delays, the cycle of output clock signal Fout is further prolonged, and the frequency thereof is further decreased. By such means, as the logic 1 of the signal Q0 passes through the latch sequence stage by stage, the frequency of the output clock signal Fout becomes lower and lower. When the signals Q1 to Q200 are all logic 1, the frequency of the output clock signal Fout is the lowest, and now the control circuit 520 sets the signal Q0 to be 0. During each of the next cycles, as the logic 0 passes through the latch sequence stage by stage, the long delays processed to the output clock signal Fin are substituted by the short delays one by one, so that the frequency of the output clock signal Fout is gradually increased. Therefore, as long as the control circuit 520 switches the signal Q0 to be logic 0 or 1 according to a certain rule, the spectrum spreading then can be achieved.
The SSCG 500 is a pure digital design, which does not include the capacitors, so that an area thereof is relatively small, though it still has defects. Due to realistic factors such as fabrication variation, fluctuation of an operation voltage, and temperature variation, etc., charging/discharging capabilities of the inverters 513 are asymmetric, namely, capabilities of the inverters 513 for pulling up and pulling down the output signal are asymmetric. After 200 stages accumulation, when the input clock signal Fin enters a high frequency region, a duty cycle of the output clock signal Fout is dramatically varied. Namely, the output clock signal Fout is seriously deformed, even is saturated to have all high voltages or low voltages (i.e., 100% or 0% duty cycle). In such case, the SSCG 500 fails to function.